QL5232-33APB456I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5232-33APB456I
QuickLogic Corporation
'QL5232-33APB456I' PDF : 18 Pages View PDF
QL5232 - QuickPCITM
Usr_Addr_WrData[31:0]
Usr_CBE[3:0]
Usr_Adr_Valid
Usr_Adr_Inc
Usr_WrReq
Usr_RdDecode
Usr_WrDecode
Usr_Select
Usr_Write
Cfg_Write
Cfg_RdData[31:0]
Usr_RdData[31:0]
PCI Target Interface
PCI Target Interface
O Target address and data from target writes. During all target
accesses, the address will be presented on
Usr_Addr_WrData[31:0] and simultaneously, Usr_Adr_Valid will
be active. During target write transactions, this port will present
write data to the PCI configuration space or user logic.
O PCI command and byte enables. During target accesses, the PCI
command will be presented on Usr_CBE[3:0] and simultaneously,
Usr_Adr_Valid will be active. During target read or write
transactions, this port will present active-low byte-enables to the
PCI configuration space or user logic.
O Indicates the beginning of a PCI transaction, and that a target
address is valid on Usr_Addr_WrData[31:0] and the PCI
command is valid on Usr_CBE[3:0]. When this signal is active,
the target address must be latched and decoded to determine if this
address belongs to the device’s memory space. Also, the PCI
command must be decoded to determine the type of PCI
transaction. On subsequent clocks of a target access, this signal
will be low, indicating that data (not an address) is present on
Usr_Addr_WrData[31:0].
O Indicates that the target address should be incremented, because
the previous data transfer has completed. During burst target
accesses, the target address is only presented to the back-end logic
at the beginning of the transaction (when Usr_Adr_Valid is
active), and must therefore be latched and incremented (by 4) for
subsequent data transfers.
O This signal will be active for the duration of a target write
transaction, and may be used by back-end logic to turn on output-
enables for transmitting the data off-chip.
I Active when a “user read” command has been decoded from the
Usr_CBE[3:0] bus. This command may be mapped from any of
the PCI “read” commands, such as Memory Read, Memory Read
Line, Memory Read Multiple, I/O Read, etc.
I Active when a “user write” command has been decoded from the
Usr_CBE[3:0] bus. This command may be mapped from any of
the PCI “write” commands, such as Memory Write or I/O Write.
I The address on Usr_Addr_WrData[31:0] has been decoded and
determined to be within the address space of the device.
Usr_Addr_WrData[31:0] must be compared to each of the valid
Base Address Registers in the PCI configuration space. Also, this
signal must be gated by the Memory Access Enable or I/O Access
Enable registers in the PCI configuration space (Command
Register bits 1 or 0 at offset 04h).
O Write enable for data on Usr_Addr_WrData[31:0] during PCI
writes.
O Write enable for data on Usr_Addr_WrData[31:0] during PCI
configuration write transactions.
I Data from the PCI configuration registers, required to be presented
during PCI configuration reads.
I Data from the back-end user logic (and/or DMA configuration
registers), required to be presented during PCI reads.
5
Rev B
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