QL6325-E-6PTN280C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL6325-E-6PTN280C' PDF : 56 Pages View PDF
QL6325E Eclipse-E Data Sheet Rev. F
Table 25: PT280 and PS484 Pin Descriptions (Continued)
Pin
Direction
Function
Description
IOCTRL(A)
I Highdrive input
This pin provides fast RESET, SET, CLOCK, and ENABLE
access to the I/O cell flip-flops, providing fast clock-to-out and
fast I/O response times. This pin can also double as a high-
drive pin to the internal logic cells. The A inside the
parenthesis means that IOCTRL is located in Bank A. There
is an internal pulldown resistor to GND on this pin. This pin
should be tied to GND if it is not used. For backwards
compatibility with Eclipse and EclipsePlus, it can be tied to
VCCIO(C) or GND. If tied to VCCIO(C), it will draw no more
than 20 µA per IOCTRL pin due to the pulldown resistor. The
voltage tolerance of this pin is specified by VCCIO(C).
PLLIN
PLLOUT
VCC
VCCIO(C)
VCCIO(A),
VCCIO(B),
VCCIO(D),
VCCIO(E),
VCCIO(F),
VCCIO(G),
VCCIO(H)
VCCPLL
PLL_RESET
I PLL clock input
Clock input for PLL. The voltage tolerance of this pin is
specified by VCCIO(C).
O PLL output pin
Dedicated PLL output pin. Must be left unconnected if the
PLL is not driven off chip. PLLOUT pin is driven by VCCIO.
For a list of each PLLOUT pin and the VCCIO pin that powers
it see Table 26.
I Power supply pin
Connect to 2.5 V supply.
This pin specifies the input voltage tolerance for CLK,
DEDCLK, PLLIN, and IOCTRL dedicated input pins, as well
as the output voltage drive TDO JTAG pins. If the PLLs are
used, VCCIO(C) must be 2.5 V or 3.3 V. The legal range for
Voltage tolerance for clocks,
VCCIO(C) is between 1.71 V and 3.6 V.
I
TDO JTAG output, and IOCTRL. This pin provides the flexibility to interface the device with
Input voltage tolerance/drive pin. either a 3.3 V, 2.5 V, or 1.8 V device. The C inside the
parenthesis means that VCCIO is located in BANK C. Every
I/O pin in Bank C will be tolerant of VCCIO input signals and
will drive VCCIO level output signals. This pin must be
connected to either 3.3 V, 2.5 V, or 1.8 V.
This pin provides the flexibility to interface the device with
either a 3.3 V, 2.5 V, or 1.8 V device. As an exmple, the A
I
Input voltage tolerance/drive pin
inside the parenthesis means that VCCIO is located in BANK
A. Every I/O pin in Bank A will be tolerant of VCCIO input
signals and will drive VCCIO level output signals. This pin
must be connected to either 3.3 V, 2.5 V, or 1.8 V.
I Power Supply pin for PLL
I PLL reset pin
Connect to 2.5 V supply. Even if your design does not utilize
the PLLs, you must connect VCCPLL to 2.5 V.
If PLL_RESET is asserted, then CLKNET_OUT and
PLLPAD_OUT are reset to 0. This signal must be asserted
and then released in order for the LOCK_DETECT to work.
If a PLL module is not used, then the associated PLLRST<x>
must be connected to VCCIO(C).
© 2005 QuickLogic Corporation
www.quicklogic.com
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