QL6325-E-6PTN280C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL6325-E-6PTN280C' PDF : 56 Pages View PDF
QL6325E Eclipse-E Data Sheet Rev. F
The rest of the PQ208 pins should be terminated at the board level in the manner presented in Table 27.
Signal Name
PLLOUT<x>a
IOCTRL<y>b
CLK/PLLIN<x>
PLLRST<x>
INREF<y>
Table 27: PQ208 Recommended Unused Pin Terminations
Recommended Termination
In earlier versions, the recommendation for unused PLLOUT pins was that they be connected to
VCC or GND. This was acceptable for Rev. D (and earlier) silicon, including all 0.25 µm devices.
For Rev. G (and later) silicon, unused PLLOUT pins should be left unconnected. Used PLLOUT
pins will normally be connected to inputs, but can also be left unconnected. For the truth table of
PLLOUT connections, refer to Table 29.
There is an internal pulldown resistor to GND on this pin. This pin should be tied to GND if it is not
used. For backwards compatibility with Eclipse, it can be tied to VDED or GND. If tied to VDED, it
will draw no more than 20 µA per IOCTRL pin due to the pulldown resistor.
Any unused clock pins should be connected to VDED or GND.
If a PLL module is not used, then the associated PLLRST<x> must be connected to VDED.
If an I/O bank does not require the use of the INREF signal the pin should be connected to GND.
a. x represents a number.
b. y represents an alphabetical character.
The rest of the PT280 and PS484 pins should be terminated at the board level in the manner presented in
Table 28.
Table 28: PT280 and PS484 Recommended Unused Pin Terminations
Signal Name
PLLOUT<x>a
IOCTRL<y>b
CLK/PLLIN<x>
PLLRST<x>
INREF<y>
Recommended Termination
In earlier versions, the recommendation for unused PLLOUT pins was that they be connected to
VCC or GND. This was acceptable for Rev. D (and earlier) silicon, including all 0.25 µm devices.
For Rev. G (and later) silicon, unused PLLOUT pins should be left unconnected. Used PLLOUT
pins will normally be connected to inputs, but can also be left unconnected. For the truth table of
PLLOUT connections, refer to Table 29.
There is an internal pulldown resistor to GND on this pin. This pin should be tied to GND if it is not
used. For backwards compatibility with Eclipse, it can be tied to VCCIO(C) or GND. If tied to
VCCIO(C), it will draw no more than 20 µA per IOCTRL pin due to the pulldown resistor.
Any unused clock pins should be connected to VCCIO(C) or GND.
If a PLL module is not used, then the associated PLLRST<x> must be connected to VCCIO(C).
If an I/O bank does not require the use of the INREF signal the pin should be connected to GND.
a. x represents a number.
b. y represents an alphabetical character.
Table 29: Recommended PLLOUT Terminations Truth Table
PLL_RESET
Recommend PLLOUT Termination
0
Must be left unconnected.
1
May be left unconnected, or connected to GND. Must not be connected to VCC.
44
•
•••
••
www.quicklogic.com
© 2005 QuickLogic Corporation
Share Link: 
