QL6325-E-6PTN280C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL6325-E-6PTN280C' PDF : 56 Pages View PDF
QL6325E Eclipse-E Data Sheet Rev. F
Figure 35: Eclipse-E Input Register Cell
QE
D
R
tISU
+
-
tSID
PAD
Symbol
tISU
tIHL
tICO
tIRST
tIESU
tIEH
Table 17: I/O Input Register Cell Timing
Parameter
Value
Min Max
Input register setup time: time the synchronous input of the flip-flop must be stable
before the active clock edge
2.15 ns
-
Input register hold time: time the synchronous input of the flip-flop must be stable after
the active clock edge
0 ns
-
Input register clock-to-out: time taken by the flip-flop to output after the active clock edge - 0.3 ns
Input register reset delay: time between when the flip-flop is “reset”(low) and when the
output is consequently “reset” (low)
-
0.82 ns
Input register clock enable setup time: time “enable” must be stable before the active
clock edge
0.4 ns
-
Input register clock enable hold time: time “enable” must be stable after the active clock
edge
0 ns
-
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