QL6325-E-8PT280I View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL6325-E-8PT280I

FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

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QL6325E Eclipse-E Data Sheet Rev. F

Table 18: I/O Input Buffer Delays

Symbol

Parameter

To get the total input delay add this delay to tISU

tSID (LVTTL) LVTTL input delay: Low Voltage TTL for 3.3 V applications

tSID (LVCMOS2)

LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower

applications

tSID (LVCMOS18) LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications

tSID (GTL+) GTL+ input delay: Gunning Transceiver Logic

tSID (SSTL3) SSTL3 input delay: Stub Series Terminated Logic for 3.3 V

tSID (SSTL2) SSTL2 input delay: Stub Series Terminated Logic for 2.5 V

tSID (PCI) PCI input delay: Peripheral Component Interconnect for 3.3 V

Value

Min

Max

-

0.82 ns

-

0.82 ns

-

-

-

0.94 ns

-

0.94 ns

-

0.94 ns

-

0.82 ns

Figure 36: Eclipse-E Input Register Cell Timing

R

CLK

D

tISU

t IHL

Q

tICO

t IRS T

E

tIESU tIEH

32

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