QL6325-E-8PT280I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL6325-E-8PT280I' PDF : 56 Pages View PDF
QL6325E Eclipse-E Data Sheet Rev. F
Power vs. Operating Frequency
The basic power equation which best models power consumption is given below:
PTOTAL = 0.350 + f[0.0031 ηLC + 0.0948 ηCKBF + 0.01 ηCLBF + 0.0263 ηCKLD +
0.543 ηRAM + 0.20 ηPLL + 0.0035 ηINP + 0.0257 ηOUTP] (mW)
Where:
ηLC is the total number of logic cells in the design
ηCKBF = # of clock buffers
ηCLBF = # of column clock buffers
ηCKLD = # of loads connected to the column clock buffers
ηRAM = # of RAM blocks
ηPLL = # of PLLs
ηINP is the number of input pins
ηOUTP is the number of output pins
NOTE: To learn more about power consumption, see QuickLogic Application Note 60 at
http://www.quicklogic.com/images/appnote60.pdf.
Power-Up Sequencing
Figure 41: Power-Up Sequencing
VCCIO
VDED
VDED2
VPUMP
VCC
VccPLL
|VCCIO, VDED, VDED2, VPUMP - VCC|MAX
VCC
400 us
Time
When powering up a device, the VCCPLL/VCC/VCCIO/VDED/VDED2 rails must take 400 µs or longer to reach
the maximum value (refer to Figure 41).
NOTE: Ramping VCCPLL, VCC, VCCIO, VPUMP, VDED, or VDED2 faster than 400 µs can cause the device to
behave improperly.
For users with a limited power budget, ensure VCCIO, VDED, VDED2, and VPUMP are within 500 mV of VCC when
ramping up the power supplies.
© 2005 QuickLogic Corporation
www.quicklogic.com
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