QL6325-E-8PT280I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL6325-E-8PT280I' PDF : 56 Pages View PDF
QL6325E Eclipse-E Data Sheet Rev. F
PT280 and PS484 Pin Descriptions
Table 25: PT280 and PS484 Pin Descriptions
Pin
Direction
Function
Description
JTAG Pin Descriptions
TDI/RSI
I
Test Data In for JTAG/RAM init.
Serial Data In
Hold HIGH during normal operation. Connects to serial
PROM data in for RAM initialization. Connect to VDED2 if
unused
TRSTB/RRO
I/0
Active low Reset for JTAG/RAM Hold LOW during normal operation. Connects to serial
init. reset out
PROM reset for RAM initialization. Connect to GND if unused
TMS
I Test Mode Select for JTAG
Hold HIGH during normal operation. Connect to VDED2 if not
used for JTAG
TCK
I Test Clock for JTAG
Hold HIGH or LOW during normal operation. Connect to
VDED2 or GND if not used for JTAG
TDO/RCO
O
Test data out for JTAG/RAM init.
clock out
Connect to serial PROM clock for RAM initialization. Must be
left unconnected if not used for JTAG or RAM initialization.
The output voltage drive is specified by VCCIO(C).
Dedicated Pin Descriptions
Low skew global clock. This pin provides access to a
dedicated, distributed network capable of driving the CLOCK,
SET, RESET, F1, and A2 inputs to the Logic Cell, READ, and
CLK
I Global clock network pin
WRITE CLOCKS, Read and Write Enables of the Embedded
RAM Blocks, CLOCK of the ECUs, and Output Enables of the
I/Os. The voltage tolerance of this pin is specified by
VCCIO(C).
DEDCLK
I Dedicated clock pin
Very low skew global clock. This pin provides access to a
dedicated, distributed clock network capable of driving the
CLOCK inputs of all sequential elements of the device (e.g.,
RAM, Flip Flops). The voltage tolerance of this pin is
specified by VCCIO(C).
GND
I Ground pin
Connect to ground.
GNDPLL
I Ground pin for PLL
Connect to GND.
INREF(A)
The INREF is the reference voltage pin for GTL+, SSTL2, and
STTL3 standards. Follow the recommendations provided in
I
Differential reference voltage
Table 12 for the appropriate standard. The A inside the
parenthesis means that INREF is located in BANK A. This pin
should be tied to GND if voltage referenced standards are not
used.
I/O(A)
I/O Input/Output pin
The I/O pin is a bi-directional pin, configurable to either an
input-only, output-only, or bi-directional pin. The A inside the
parenthesis means that the I/O is located in Bank A. If an I/O
is not used, SpDE (QuickWorks Tool) provides the option of
tying that pin to GND, VCC, or TriState.
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