QL7100-7PT208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL7100-7PT208C' PDF : 42 Pages View PDF
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WCLK
WA
tSWA
tHWA
WD
tSWD
tHWD
WE
tSWE
tHWE
RD
old data
new data
tWCRD
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tSRA
RA setup time to RCLK: time the READ ADDRESS must be stable before the active
edge of the READ CLOCK
0.686 ns
-
tHRA
RA hold time to RCLK: time the READ ADDRESS must be stable after the active
edge of the READ CLOCK
0 ns
-
tSRE
RE setup time to WCLK: time the READ ENABLE must be stable before the active
edge of the READ CLOCK
0.243 ns
-
tHRE
RE hold time to WCLK: time the READ ENABLE must be stable after the active
edge of the READ CLOCK
0 ns
-
tRCRD
RCLK to RD: time between the active READ CLOCK edge and the time when the
data is available at RD
-
4.38 ns
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rPDRD
RA to RD: time between when the READ ADDRESS is input and when the DATA
is output
-
2.06 ns
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