QL7100-7PT208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL7100-7PT208C' PDF : 42 Pages View PDF
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Input register setup time: time the synchronous input of the flip-flop must be stable
before the active clock edge
3.12 ns
-
Input register hold time: time the synchronous input of the flip-flop must be stable
after the active clock edge
0 ns
-
Input register clock-to-out: time taken by the flip-flop to output after the active clock
edge
- 1.08 ns
Input register reset delay: time between when the flip-flop is “reset” (low) and when
the output is consequently “reset” (low)
- 0.99 ns
Input register clock enable setup time: time “enable” must be stable before the
active clock edge
0.37 ns
-
Input register clock enable hold time: time “enable” must be stable after the active
clock edge
0 ns
-
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