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tSID (LVTTL)
tSID (LVCMOS2)
LVTTL input delay: Low Voltage TTL for 3.3 V applications
LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower
applications
tSID (GTL+)
tSID (SSTL3)
tSID (SSTL2)
GTL+ input delay: Gunning Transceiver Logic
SSTL3 input delay: Stub Series Terminated Logic for 3.3 V
SSTL2 input delay: Stub Series Terminated Logic for 2.5 V
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- 0.42 ns
- 0.68 ns
- 0.55 ns
- 0.61 ns
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