RC28F320J3F75 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
'RC28F320J3F75' PDF : 66 Pages View PDF
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Table 6: Power-Up/Down Sequence
Power Supply
Voltage
Power-Up Sequence
VCC(min)
VCCQ(min)
VPEN(min)
1st
1st
3rd
2nd
2nd(1)
1st(1)
Sequencing not
required(1)
2nd
3rd
2nd
1st
Note:
1.
Power supplies connected or sequenced together.
Power-Down Sequence
2nd
1st(1)
2nd(1)
1st
Sequencing not
required(1)
Device inputs must not be driven until all supply voltages reach their minimum range.
RP# should be low during power transitions.
5.3.2
Power Supply Decoupling
When the device is enabled, many internal conditions change. Circuits are energized,
charge pumps are switched on, and internal voltage nodes are ramped. All of this
internal activities produce transient signals. The magnitude of the transient signals
depends on the device and system loading. To minimize the effect of these transient
signals, a 0.1 µF ceramic capacitor is required across each VCC/VSS and VCCQ signal.
Capacitors should be placed as close as possible to device connections.
Additionally, for every eight flash devices, a 4.7 µF electrolytic capacitor should be
placed between VCC and VSS at the power supply connection. This 4.7 µF capacitor
should help overcome voltage slumps caused by PCB trace inductance.
5.4
Reset
By holding the flash device in reset during power-up and power-down transitions,
invalid bus conditions may be masked. The flash device enters reset mode when RP# is
driven low. In reset, internal flash circuitry is disabled and outputs are placed in a high-
impedance state. After return from reset, a certain amount of time is required before
the flash device is able to perform normal operations. After return from reset, the flash
device defaults to asynchronous page mode. If RP# is driven low during a program or
erase operation, the program or erase operation will be aborted and the memory
contents at the aborted block or address are no longer valid. See Figure 12, “AC
Waveform for Reset Operation” on page 28 for detailed information regarding reset
timings.
Datasheet
20
Jan 2011
208032-03
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