SAA7392HLM2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HLM2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.9 Serial output interface
The serial data output interface consists of three signals:
WCLK (word select), BCLK (serial clock), DATAO (serial
data). The polarity of WCLK and the data can be inverted.
The FLAG signal is used to identify if there are errors in
either the LSB or MSB of the 16-bit data word. The
interface can be used as a master or slave interface (BCLK
and WCLK are then inputs), selectable by register
Output1.
The serial data interface can be switched into two modes:
Philips I2S and the EIAJ format (the protocol can use either
16, 24 or 32 BCLK clocks for each 16-bit output,
selectable by Output1 register). The formats are shown in
Figs 11 to 16.
The BCLK frequency can be selected by register
ClockPre, or input externally. If the data out rate does not
correspond with the disc speed and the bit clock data, the
FIFO will either fill or empty. FIFO underflow (STOPCK
output goes HIGH indicating absence of data) must be
avoided. If BCLK is an input, it should be stopped and
restarted again when STOPCK goes LOW. If BCLK is
output, it is automatically stopped if BCLK gate enable is
set (via register ClockPre); if it is not set then unpredictable
operation will result.
handbook, full pagewidth
BCLK
DATA D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
FLAG
FLAG - MSB (1 is unreliable)
FLAG - LSB
WCLK
left
right
SYNC
Fig.11 Format 1: 16 clocks/word I2S format.
MGR800
handbook, full pagewidth
BCLK
DATA D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
FLAG
FLAG - MSB (1 is unreliable)
FLAG - LSB
WCLK
right
left
SYNC
MGR801
Fig.12 Format 2: 16 clocks/word ‘S’ format (WCLK inverted).
2000 Mar 21
34
Share Link: 
