Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
Table 74 Selection of coefficient Ki
Ki.1
Ki.0
0
0
3.1 × 10−5
0
1
6.1 × 10−5
1
0
1.2 × 10−4
1
1
2.4 × 10−4
COEFFICIENT Ki
Table 75 Selection of the coefficient Kf
Kf.2
Kf.1
Kf.0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
reserved
3.7 × 10−9
7.5 × 10−9
1.5 × 10−8
3.0 × 10−8
6.0 × 10−8
1.2 × 10−7
2.4 × 10−7
COEFFICIENT Kf
7.10.3 MOTOR CONTROL REGISTER 7 (MOTOR7)
Table 76 Motor Control Register 7 (address 1DH) - WRITE
7
6
PhErSrc
−
5
Kf’.2
4
Kf’.1
3
Kf’.0
2
Ki’.2
1
Ki’.1
0
Ki’.0
Table 77 Description of Motor7 bits
BIT
SYMBOL
DESCRIPTION
7
PhErSrc
If PhErSrc = 0, then the phase error source is FIFOFil. If PhErSrc = 1, then the phase
error source is XError.
6
−
This bit is reserved.
5
Kf’.2
4
Kf’.1
3
Kf’.0
These 3 bits select the value of the Kf’ coefficient; see Table 78.
Kf’ operates by sampling the input. For example, for Kf’ = 1, every sample of the input is
passed through to a following integrator circuit, for a Kf’ of 0.5 every 2nd sample is
passed through, for a Kf’ of 0.25 every 4th sample is passed through, and so on.
For a DC input signal, Kf × Kf’ should always give the same result. If however, the input
is varying sufficiently quickly, the Kf × Kf’ combinations with the same product will not
always give the same result, especially for low values of Kf’, where the sampling in the
extreme becomes 1 out of every 128 samples. (The input samples to the block that
performs the Kf’ multiplication occur at a rate of 1 sample every 24 system clock
periods.)
2
Ki’.2
1
Ki’.1
These 3 bits select the value of the Ki’ coefficient; see Table 78.
0
Ki’.0
2000 Mar 21
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