SAA7392HLM2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HLM2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.12.3 SUBCODE CONFIGURATION REGISTER 2 (SUBCONFIG2)
Table 99 Subcode Configuration Register 2 (address 24H) - READ/WRITE
7
BSwOn
6
InOBO
5
relcnt.2
4
relcnt.1
3
relcnt.0
2
curcnt.2
1
curcnt.1
0
curcnt.0
Table 100 Description of SubConfig2 bits
BIT
7
6
5 to 3
2 to 0
SYMBOL
DESCRIPTION
BSwOn If BSwOn = 0, then no bank switching. If BSwOn = 1, then bank switch will occur when
first subcode sync output by EFM modulator and curcnt<2:0> = 000
InOBO
If InOBO = 0, then original bank is used again. In this case no bank switching or
interrupts occur and automatic bank update is still done on the original bank, even when
the other bank is output. If InOBO = 1, then the other bank is automatically inserted
once into Q-channel, this bit is automatically reset to logic 0.
relcnt<2:0> Count value to load curcnt<2:0>.
curcnt<2:0> Current value of subcode frame counter.
7.12.4 SUBCODE START DATA REGISTER (SUBSTARTDATA)
Table 101 Subcode Start Data Register (address 25H) - WRITE
7
6
5
4
3
2
1
0
NextSet
−
−
−
−
−
−
−
Table 102 Description of SubStartData bits
BIT
7
6 to 0
SYMBOL
NextSet
−
DESCRIPTION
If NextSet = 0, then access other bank. If NextSet = 1, then access current bank that is
being used for Q-channel data.
These 7 bits are reserved.
7.12.5 SUBCODE DATA REGISTER (SUBDATA)
Sub-CPU read/write from/to the SubData register causes a read or write to occur on the Q-code memory. Normally the
sub-CPU would access all 10 bytes of a Q-code bank. Before such a block access the sub-CPU must issue a write to
the SubStartWrite register.
Table 103 Subcode Data Register (address 26H) - READ/WRITE
7
QCD.7
6
QCD.6
5
QCD.5
4
QCD.4
3
QCD.3
2
QCD.2
1
QCD.1
0
QCD.0
2000 Mar 21
49
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