SAA7392HLM2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HLM2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.10.1 MOTOR CONTROL REGISTER 1 (MOTOR1)
The frequency/tacho set-point (i.e. the target PLL or tacho frequency) is calculated as follows:
Frequency set-point =
1
–
M------F---S-2---5<---6-7---:--0--->--
× 2.667 × ADC clock
PLL
frequency
=
P-----L---L---F----r--e1---q2----R8----<---7----:-0---->--
× ADC
clock
Note that: (PLL frequency − frequency set-point) must be less than 1.33 × ADC clock.
Table 70 Motor Control Register 1 (address 0CH) - WRITE
7
MFS.7
6
MFS.6
5
MFS.5
4
MFS.4
3
MFS.3
2
MFS.2
1
MFS.1
0
MFS.0
7.10.2 MOTOR CONTROL REGISTER 2 (MOTOR2)
Table 71 Motor Control Register 2 (address 0DH) - WRITE
7
6
5
4
3
2
1
0
G.2
G.1
G.0
Ki.1
Ki.0
Kf.2
Kf.1
Kf.0
Table 72 Description of Motor2 bits
BIT
SYMBOL
DESCRIPTION
7
G.2
These 3 bits select coefficient G; see Table 73.
6
G.1
5
G.0
4
Ki.1
These 2 bits select coefficient Ki; see Table 74.
3
Ki.0
In order to set the integrator bandwidth low enough at high system clock speeds, an
extra divider for Ki has been added. This is set by writing to register Motor7. The
resulting Ki(tot) is then the Ki set by Motor2 multiplied by the Ki’ set by Motor7.
2
Kf.2
These 3 bits select coefficient Kf; see Table 75.
1
Kf.1
0
Kf.0
Table 73 Selection of coefficient G
G.2
G.1
G.0
0
0
0
8.36
0
0
1
10.4
0
1
0
16.7
0
1
1
20.9
1
0
0
33.4
1
0
1
41.8
1
1
0
66.9
1
1
1
83.6
COEFFICIENT G
2000 Mar 21
40
Share Link: 
