SC103335VR400B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'SC103335VR400B' PDF : 72 Pages View PDF
2. Minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit
as shown in the PCI Local Bus Specification.
3. REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have
a setup of 5 ns at 66 MHz. All other signals are bused.
4. See the timing measurement conditions in the PCI Local Bus Specification.
For Measurement and Test Conditions, see the PCI Local Bus Specification.
1.3.8 Local Plus Bus
The Local Plus Bus is the external bus interface of the MPC5200B. A maximum of eight configurable chip selects (CS) are
provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and MUXED. The reference clock is the
PCI CLK. The maximum bus frequency is 66 MHz.
Definition of Acronyms and Terms:
• WS = Wait State
• DC = Dead Cycle
• LB = Long Burst
• DS = Data Size in Bytes
• tPCIck = PCI clock period
• tIPBIck = IPBI clock period
PCI CLK
tPCIck
IPBI CLK
tIPBIck
Figure 10. Timing Diagram—IPBI and PCI clock (example ratio: 4:1)
1.3.8.1 Non-MUXed Mode
Table 24. Non-MUXed Mode Timing
Sym
Description
t CSA
t CSN
t1
t2
t3
t4
t5
t6
t7
t8
t9
PCI CLK to CS assertion
PCI CLK to CS negation
CS pulse width
ADDR valid before CS assertion
ADDR hold after CS negation
OE assertion before CS assertion
OE negation before CS negation
RW valid before CS assertion
RW hold after CS negation
DATA output valid before CS assertion
DATA output hold after CS negation
Min
4.6
2.9
(2 + WS) × tPCIck
tIPBIck
tIPBIck
—
—
tPCIck
tIPBIck
tIPBIck
tIPBIck
Max
10.6
7.0
(2 + WS) × tPCIck
tPCIck
—
4.8
2.7
—
—
—
—
Units Notes SpecID
ns
—
A7.1
ns
—
A7.2
ns
(1)
A7.3
ns
—
A7.4
ns
(2)
A7.5
ns
—
A7.6
ns
—
A7.7
ns
—
A7.8
ns
—
A7.9
ns
— A7.10
ns
— A7.11
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
23
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