PCI CLK
CS [ x]
ADDR
OE
R/W
DATA (wr)
DATA (rd)
ACK
TS
TSIZ[1:2]
t1
t2
t3
t4
t5
t6
t7
t8
t9
t12
t14
t15
t10
t19
t18
t11
t13
t17
t16
Figure 11. Timing Diagram—Non-MUXed Mode
1.3.8.2 Burst Mode
Table 25. Burst Mode Timing
Sym
t CSA
t CSN
t1
Description
PCI CLK to CS assertion
PCI CLK to CS negation
CS pulse width
t2
ADDR valid before CS assertion
t3
ADDR hold after CS negation
t4 OE assertion before CS assertion
t5
OE negation before CS negation
t6
RW valid before CS assertion
t7
RW hold after CS negation
t8
DATA setup before rising edge of
PCI clock
Min
4.6
2.9
(1 + WS + 4LB × 2
× (32/DS)) × tPCIck
tIPBIck
–0.7
—
—
tPCIck
tPCIck
3.6
Max
Units Notes SpecID
10.6
7.0
(1 + WS + 4LB × 2 ×
(32/DS)) × tPCIck
tPCIck
—
4.8
2.7
—
—
—
ns — A7.22
ns — A7.23
ns (1),(2) A7.24
ns — A7.25
ns — A7.26
ns — A7.27
ns — A7.28
ns — A7.29
ns — A7.30
ns — A7.31
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
25