SC103335VR400B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'SC103335VR400B' PDF : 72 Pages View PDF
Table 24. Non-MUXed Mode Timing (continued)
Sym
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
Description
DATA input setup before CS negation
DATA input hold after CS negation
ACK assertion after CS assertion
ACK negation after CS negation
TS assertion before CS assertion
TS pulse width
TSIZ valid before CS assertion
TSIZ hold after CS negation
ACK change before PCI clock
ACK change after PCI clock
Min
8.5
0
tPCIck
—
—
tPCIck
tIPBIck
tIPBIck
—
—
Max
—
(DC + 1) × tPCIck
—
tPCIck
6.9
tPCIck
—
—
2.0
4.4
Units Notes SpecID
ns
— A7.12
ns
(6) A7.13
ns
(3) A7.14
ns
(3) A7.15
ns
(4) A7.16
ns
(4) A7.17
ns
(5) A7.18
ns
(5) A7.19
ns
(1) A7.20
ns
(1) A7.21
NOTES:
1. ACK can shorten the CS pulse width.
Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from
0–65535.
2. In Large Flash and MOST Graphics mode the shared PCI/ATA pins, used as address lines, are released at the same moment
as the CS. This can cause the address to change before CS is deasserted.
3. ACK is input and can be used to shorten the CS pulse width.
4. Only available in Large Flash and MOST Graphics mode.
5. Only available in MOST Graphics mode.
6. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration
happens the bus can be driven within 4 IPB clocks by an other modules.
MPC5200B Data Sheet, Rev. 4
24
Freescale Semiconductor
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