SC103335VR400B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'SC103335VR400B' PDF : 72 Pages View PDF
1.3.8.3 MUXed Mode
Table 26. MUXed Mode Timing
Sym
t CSA
t CSN
tALEA
t1
t2
t3
t4
t5
t6
t7
tTSA
t8
t9
tOEA
tOEN
t10
t11
t12
t13
t14
t15
t16
Description
Min
Max
Units Notes SpecID
PCI CLK to CS assertion
4.6
10.6
ns
PCI CLK to CS negation
2.9
7.0
ns
PCI CLK to ALE assertion
—
3.6
ns
ALE assertion before Address, Bank,
—
TSIZ assertion
5.7
ns
CS assertion before Address, Bank,
—
TSIZ negation
–1.2
ns
CS assertion before Data wr valid
—
–1.2
ns
Data wr hold after CS negation
Data rd setup before CS negation
tIPBIck
8.5
—
ns
—
ns
Data rd hold after CS negation
ALE pulse width
CS assertion after TS assertion
0
(DC + 1) × tPCIck ns
—
tPCIck
ns
—
6.9
ns
TS pulse width
—
tPCIck
ns
CS pulse width
(2 + WS) × tPCIck (2 + WS) × tPCIck ns
OE assertion before CS assertion
—
4.7
ns
OE negation before CS negation
—
5.9
ns
RW assertion before ALE assertion
RW negation after CS negation
ACK assertion after CS assertion
ACK negation after CS negation
ALE negation to CS assertion
ACK change before PCI clock
tIPBIck
—
tIPBIck
—
—
—
—
ns
tPCIck
ns
—
ns
tPCIck
ns
tPCIck
ns
2.0
ns
ACK change after PCI clock
—
4.4
ns
— A7.39
— A7.40
— A7.41
— A7.42
— A7.43
—
—
—
(1),(3)
—
—
—
—
—
—
—
—
(2)
(2)
(2)
(2)
A7.44
A7.45
A7.46
A7.47
A7.48
A7.49
A7.50
A7.51
A7.52
A7.53
A7.54
A7.55
A7.56
A7.57
A7.58
A7.59
A7.60
NOTES:
1. ACK can shorten the CS pulse width.
Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from
0–65535.
2. ACK is input and can be used to shorten the CS pulse width.
3. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration
happens the bus can be driven within 4 IPB clocks by an other modules.
MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
27
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