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SPEAR300-2 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'SPEAR300-2' PDF : 83 Pages View PDF
SPEAr300
Architecture overview
2.18
I2S interface
The I2S interface is very similar to the TDM block, but the frame sync is limited to Philips I2S
definition. It is composed of 4 signals:
I2S_LRCK; Left and right channels synchronization (Master/slave)
I2S_CLK: I2S clock (Master/slave)
I2S_DIN: I2S clock (Master/slave)
I2S DOUT: I2S output (tri-state)
The DOUT line can be high impedance when out of samples. Data is always stored in 32 bit
format in the buffer. A shift left operation is possible to left align the data.
Main features:
Can be master or slave for the clock and sync signals
Buffering of up to 1024 samples (512 left and 512 right samples representing 64 ms of
voice). Data is stored always on 32 bits.
Left and right channels are stored in two different buffers.
Two banks are used to exchange data with the processor.
In master mode, LRCK can be adjusted for 8, 16 or 32 bits width.
Data width can be less than LRCK width. Input (received on I2S_DIN) and output
(transmitted on DOUT) can be 8, 16 or 32 bits.
2.19
GPIOs
The General Purpose Input/Outputs (GPIOs) provide programmable inputs or outputs.
Main features:
Individually programmable input/output pins implemented in 3 blocks:
– Up to 6 base GPIOs in the basic subsystem (basGPIO)
– Up to 18 GPIOs in the RAS subsystem (G10 and G8)
– Up to 18 GPIOs in the keyboard controller
– Up to 8 GPIOs in the independent GPIO block (GPIO[7:0])
Programmable interrupt generation capability up to 22 pins.
Base GPIOs and independent GPIOs support bit masking in both read and write
operation through address lines.
Up to 62 general purpose I/Os are available in Mode 4 (LEND_IP_ph) (see Table 10).
In this mode the application can use:
– 10 GPIOs in G10 block
– 8 GPIOs in G8 block (0 to 3 in output mode only)
– 18 GPIO (keyboard controller I/Os in GPIO mode)
6 base GPIOs (basGPIO) (enabled as alternate functions (see Table 11)
– 8 IT pins (input only, with interrupt capability)
– 4 SYNC outputs (SYNC4-7)
– 8 SPI_I2C outputs
Doc ID 16324 Rev 2
21/83
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