SPEAR300-2 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
SPEAR300-2
STMicroelectronics
'SPEAR300-2' PDF : 83 Pages View PDF
Architecture overview
SPEAr300
2.26
USB2 device controller
Main features:
● Supports the 480 Mbps high-speed mode (HS) for USB 2.0, as well as the 12 Mbps
full-speed (FS) and the 1.5 Mbps low-speed (LS modes) for USB 1.1
● Supports 16 physical endpoints, which can be assigned to different interfaces and
configurations to implement logical endpoints
● Integrated USB transceiver (PHY)
● Local 4 Kbyte FIFO shared by all endpoints
● DMA mode and slave-only mode are supported
● In DMA mode, the UDC supports descriptor-based memory structures in application
memory
● In both modes, an AHB slave is provided by UDC-AHB, acting as programming
interface to access to memory-mapped control and status registers (CSRs)
● An AHB master for data transfer to system memory is provided, supporting 8, 16, and
32-bit wide data transactions on the AHB bus
● A USB plug detect (UPD) which detects the connection of a cable.
2.27
JPEG (CODEC)
SPEAr300 provides a JPEG CODEC with header processing (JPGC), able to decode (or
encode) image data contained in the RAM memory, from the JPEG (or MCU) format to the
MCU (or JPEG) format.
Main features:
● Compliance with the baseline JPEG standard (ISO/IEC 10918-1)
● Single-clock per pixel encoding/decoding
● Support for up to four channels of component color
● 8-bit/channel pixel depths
● Programmable quantization tables (up to four)
● Programmable Huffman tables (two AC and two DC)
● Programmable minimum coded unit (MCU)
● Configurable JPEG headers processing
● Support for restart marker insertion
● Use of two DMA channels and of two 8 x 32-bits FIFO’s (local to the JPEG) for efficient
transferring and buffering of encoded/decoded data from/to the CODEC core.
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Doc ID 16324 Rev 2
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