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SPEAR300-2 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
'SPEAR300-2' PDF : 83 Pages View PDF
SPEAr300
Architecture overview
2.28
Cryptographic co-processor (C3)
Main features:
Supported cryptographic algorithms:
– Advanced encryption standard (AES) cipher in ECB, CBC, CTR modes
– Data encryption standard (DES) cipher in ECB and CBC modes.
– SHA-1, HMAC-SHA-1, MD5, HMAC-MD5 digests.
Instruction driven DMA based programmable engine.
AHB master port for data access from/to system memory.
AHB slave port for co-processor register accesses and initial engine-setup
The co-processor is fully autonomous (DMA input reading, cryptographic operation
execution, DMA output writing) after being set up by the host processor
The co-processor executes programs written by the host in memory, it can execute an
unlimited list of programs.
The co-processor supports hardware chaining of cryptographic blocks for optimized
execution of data-flow requiring multiple algorithms processing over the same set of
data (for example encryption + hashing on the fly)
2.29
8-channel ADC
Main features:
Successive approximation conversion method
10-bit resolution @1 Msps
Hardware supporting up to 13.5 bits resolution at 8 ksps by oversampling and
accumulation
Eight analog input (AIN) channels, ranging from 0 to 2.5 V
INL ± 1 LSB, DNL ± 1 LSB
Programmable conversion speed, (min. conversion time is 1 s)
Programmable average results from 1 (no averaging) up to 128
Programmable auto scan for all the eight channels.
Normal or enhanced mode;
– In normal mode the conversion start upon CPU request
– In enhanced mode the ADC converts continuously the selected channels inserting
a selectable amount of time between two conversions.
2.30
1-bit DAC
The one-bit DAC is a second-order noise shaper based on the TDM hardware. The action
memory determines whether a new sample needs to be sent to the DAC during the next
byte. Samples are read from the buffer memory.
Doc ID 16324 Rev 2
27/83
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