ST18AU1_DS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18AU1_DS' PDF : 87 Pages View PDF
ST18-AU1
9.2.3 Control registers
Three 16-bit control registers are dedicated to the DMA controller interface. These are the
general control register, the address interrupt control register and the mask sensitivity control
register. They are detailed below.
DGC: General control register
Three bits are dedicated for each DMA channel (bits 0 to 2 to channel 0, bits 4 to 6 to channel
1, bits 8 to 10 to channel 2, bits 12 to 14 to channel 3).
(Address = 0040, Reset = 0000h, Read/Write).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- DRW DBC DBC - DRW DBC DBC - DRW DBC DBC - DRW DBC DBC
310
210
110
010
Bit
DBC1/DBC0
DRWi
Function
Bus choice for data transfer
00: X-bus (default)
01: Y-bus
10: I-bus
11: reserved
Data transfer direction
0: Write access (default)
1: Read access
DAIC: Address/interrupt control register
Four bits are dedicated for each DMA channel (bits 0 to 3 to channel 0, bits 4 to 7 to channel
1, bits 8 to 11 to channel 2, bits 12 to 15 to channel 3).
(Address = 0042, Reset = 0000h, Read/Write)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAI3 DLA3 DIP3 DIE3 DAI2 DLA2 DIP2 DIE2 DAI1 DLA1 DIP1 DIE1 DAI0 DLA0 DIP0 DIE0
Bit
Function
DIEi
Enable interrupt
0: Interrupt request output associated to channel i is masked (default)
1: Interrupt request output associated to channel i is not masked
DIPi
Interrupt pending
0: No pending interrupt on channel i (default)
1: Pending interrupt on channel i (enabled if DIP_ENA input is high)
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