ST18D952 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18D952' PDF : 67 Pages View PDF
ST18952
DGC: General control register
Three bits are dedicated for each DMA channel (bits 0 to 2 to channel 0, bits 4 to 6 to channel
1, bits 8 to 10 to channel 2, bits 12 to 14 to channel 3).
(Address = 0040, Reset = 0000h, Read/Write).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- DRW3 DBC1 DBC0 - DRW2 DBC1 DBC0 - DRW1 DBC1 DBC0 - DRW0 DBC1 DBC0
Bit
DBC1/DBC0
DRWi
Function
Bus choice for data transfer
00: X-bus (default)
01: Y-bus
10: I-bus
11: reserved
Data transfer direction
0: Write access (default)
1: Read access
DAIC: Address/interrupt control register
Four bits are dedicated for each DMA channel (bits 0 to 3 to channel 0, bits 4 to 7 to channel
1, bits 8 to 11 to channel 2, bits 12 to 15 to channel 3).
(Address = 0042, Reset = 0000h, Read/Write)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAI3 DLA3 DIP3 DIE3 DAI2 DLA2 DIP2 DIE2 DAI1 DLA1 DIP1 DIE1 DAI0 DLA0 DIP0 DIE0
Bit
DIEi
DIPi
DLAi:
DAIi
Function
Enable interrupt
0: Interrupt request output associated to channel i is masked (default)
1: Interrupt request output associated to channel i is not masked
Interrupt pending
0: No pending interrupt on channel i (default)
1: Pending interrupt on channel i (enabled if DIP_ENA input is high)
Load address
0: DCAi content incremented after each data transfer (default)
1: DCAi content loaded with DIA content if DCCi value is 0,
or DCAi content incremented if DCCi value is not equal to 0
Address increment
0: DCAi content unchanged (default)
1: DCAi content modified according to DLAi state
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