ST18D952 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18D952' PDF : 67 Pages View PDF
ST18952
IMR: Interrupt mask/sensitivity register
(Address = 0029, Reset = 5555h, Read/Write)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IS7 IM7 IS6 IM6 IS5 IM5 IS4 IM4 IS3 IM3 IS2 IM2 IS1 IM1 IS0 IM0
Bit
Function
IM
Interrupt mask
0: Interrupt is not masked
1: Interrupt is masked (default)
IS
Sensitivity
0: ITRQ is active on a low level (default)
1: ITRQ is active on a falling edge
Each interrupt input ITRQ0-7 can be masked individually when the corresponding IM0-7 bit is
set. In this case any activity on the ITRQ0-7 pin is ignored. All IM bits are set during DSP reset.
ITRQ0-7 is active either on a low level when IS0-7 is low (by default on reset) or on a falling
edge when IS0-7 is high.
When ITRQ0-7 is active on a low level, it must stay low until the ITACK falling edge is sampled.
IPR: Interrupt priority register
(Address = 002A, Reset = 0000h, Read/Write))
15 14 13 12 11 10 9 8 7 6
IP7(1:0) IP6(1:0) IP5(1:0) IP4(1:0) IP3(1:0)
Bit
Function
IP
Interrupt priority level (0, 1, 2 or 3) (default is 0)
54
IP2(1:0)
32
IP1(1:0)
10
IP0(1:0)
The IPR register contains the priority level of each ITRQ0-7 interrupt input. IP0-7 priority level
is coded using two bits. The different values of IP are 0, 1, 2, 3 (0 lowest priority, 3 highest
priority).
When two ITRQ with the same priority level are requesting during the same cycle, the first
acknowledged interrupt is the one corresponding to the lowest number (for example, ITRQ0
acknowledged prior to ITRQ3).
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