ST18D952 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18D952' PDF : 67 Pages View PDF
ST18952
The current priority levels available are shown in below.
Priority level
-1
0
1
2
3
Reserved
Coding
111
000
001
010
011
100 - 110
Acceptable IT level priority
0,1,2,3
1,2,3
2,3
3
An interrupt request is acknowledged when its priority level (coded in the IPR register) is higher
than the current priority level. In this case, the current priority level becomes the interrupt
priority level and the previous current priority level is pushed onto the stack and displayed as
stack priority level (SPL)1.
The process is repeated over a range of four interrupt requests and the four previous current
stack priority levels are displayed on SPL1, SPL2, SPL3 and SPL4. If less than four interrupts
are pushed onto the stack, the unused SPL words are set to ‘000’. At the end of the interrupt
routine, the priority levels are popped from the stack.
The empty stack (ES) flag is used to indicate whether the stack is used or not. The ISP word
of the ISP register indicates the depth of the stack (see below).
Figure 8.2
ICR and ISPR Operation
INTERRUPT LEVEL 2
INTERRUPT LEVEL 3
PROGR AM
IT2
PROGRAM IT2
IT3
PROGRAM IT3
ICR
SPL4 SPL3 SPL2 SPL1 ES CPL
X X X X 1 -1
ISPR
ISP
0
SPL4 SPL3 SPL2 SPL1 ES CPL
X X X -1 0 2
ISP
1
SPL4 SPL3 SPL2 SPL1 ES CPL
X X -1 2 0 3
ISP
2
28/66
Share Link: 
