ST18952
TUD
TLE
TCS
TIE
TCM
TFP(3:0)
Bits 10-11
Bits 12-15
Timer up/down counting (bit 1)
• When TUD = ‘0’, the TIM is counting ‘down’ (reset value), i.e. the TCVR current value
register content is decremented.
• When TUD = ‘1’, the TIM is counting ‘up’, i.e. the TCVR current value register content
is incremented.
Timer load enable (bit 2)
• When the counter has reached its end value (TCVR = TEVR), TCVR is (re)loaded
with TSVR (‘start value’) register content when TLE = ‘1’.
• When TLE = ‘0’ (reset value), the next state of TCVR depends on the TCS bit.
Timer continue/stop (bit 3)
• When TLE = ‘0’ (no load) and when the counter has reached its end value (TCVR =
TEVR), the TCVR content continues to increment/decrement according to TUD bit
when TCS = ‘1’ (continue mode).
• When TCS = ‘0’ (stop mode - reset value), TCVR is stopped and content is frozen.
Timer interrupt enable (bit 4)
• When the counter has reached its end value (TCVR = TEVR), an interrupt request is
generated on TIR output when TIE = ‘1’.
• When TIE = ‘0’ (reset value), TIR output is disabled (=‘1’).
Timer cock mode (bit 5)
• When TCM = ‘0’ (reset value), the TCVR clock is derived from internal MCLK clock
according to TFP bits.
• When TCM = ‘1’, the TCVR clock is the external ECLK clock.
Timer frequency prescaler (bits 9-4; TFP(3) = msb)
• When TCM = ‘0’ (internal clock), the TCVR register clock is derived from the MCLK
clock input by dividing MCLK by 2(2+ TFP).
The coding is as follows:
TFP = 0h
prescaler by 2 (reset value) MCLK divided by 4
TFP = 1h
prescaler by 4 MCLK divided by 8
TFP = 2h
prescaler by 8 MCLK divided by 16
-...
TFP = Fh
prescaler by 216MCLK divided by 217
RESERVED and must be written as’0’
Unused and read as’0’
TSVR0-1: Timer start value register
(Address = 0059/005D, Reset value = 0000 h, Read/Write)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSV TSV TSV TSV TSV TSV TSV TSV TSV TSV TSV TSV TSV TSV TSV TSV
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Bit
TSV(15:0)
Function
Timer start value (bits15-0, TSV15 is msb
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