ST18D952 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18D952' PDF : 67 Pages View PDF
ST18952
Bit
SMS
Function
SIO Mode select: Must be set to 0 (normal mode)
SSM
SWN(2:0)
STIE
SRIE
SMEM
SLL
Bits 15-14
SIO Frame synchro mode
The SFS frame synchro is generated one clock cycle before the first data of the frame
(delayed mode) when SSM = ‘0’ (reset value) or when first data is transmitted/received
(non-delayed mode) when SSM = ‘1’.
SIO word number (SWN(2) = msb)
SWN determines the number of words inserted in the frame (up to 8). The coding is as
follows:
SWN = “0” -> 1 time slot
SWN = “1” -> 2 time slots
...
SWN = “7” -> 8 time slots
The reset value is SWN = “0”
SIO Transmit interrupt enable
• When STIE = ‘1’, interrupt request generated on the STI output when STDE flag = ‘1’.
• When STIE = ‘0’ (reset value), the STI output is disabled (‘1’)
SIO Receive interrupt enable
• When SRIE = ‘1’, interrupt request generated on SRI output when the SRDF flag = ‘1’.
• When SRIE = ‘0’ (reset value), the SRI output is disabled (‘1’)
SIO Microwire enable: Must be set to 0 (normal mode)
SIO Local loop
• When SLL = ‘1’, the STD output is internally linked to the SRD input. This allows the
SIO behavior to be checked without providing data on the SRD input.
• When SLL = ‘0’ (reset value), the SRD input is enabled
Unused and are read as ‘0’
SCR writes must be made when the SIO is disabled (SEN bit of the SIO enable register is
‘0’)SMS:
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