ST18D952 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18D952' PDF : 67 Pages View PDF
ST18952
SCOR: SIO sequence control register
(SIO0 Address = 0070h, reset value = 0000h, read/write)
(SIO1 Address = 00F0 h, reset value = 0000h, read/write)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(0)
SEQ(1:0)
Bit
SEQ(1:0)
Bits 2-15
Function
Four SIO sequences (defining the time slots order) are available:
SEQ=00
Data/Data/Data/Data
SEQ=01
Data/Control/Data/Control
SEQ=10
Data/Data/Control/Control
SEQ=11
Control/Control/Control/Control
Data time slots are transferred using the DMA controller, and control time slots are trans-
ferred using SIO buffers.
Unused and read as ‘0’
SCR: SIO control register
(SIO0 address = 0062h, reset value = 0000h, read/write)
(SIO1 address = 00E2h, reset value = 0000h, read/write)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(0)
SLL SMEN SRIE STIE
SWN(2:0)
SSM SSAL SSL SCE SCSD SWL SMS
00
0
0
1
1
011
0
0
0
0
0
0
0
Bit
SMS
SWL
SCSD
SCE
SSL
SSAL
Function
SIO Mode select: Must be set to 0 (normal mode)
SIO Word length
SWL = ‘0’
Word length is 16 bits (reset value)
SWL = ‘1’
Word length is 8 bits
SIO Clock/synchro direction
Determines whether SCK clock and SFS frame synchro signals are generated externally
or internally
SCSD = ‘0’
Generated externally (reset value)
SCSD = ‘1’
Generated internally
SIO Clock edge
SCE = ‘0’
SCE = ‘1’
SCK rising edge active (reset value)
SCK falling edge active
SIO Frame syncro length
Generated in a bit-length manner (active for one clock cycle) when SSL=’0’ (reset value)
or in a word-length manner (active for 8 or 16 clock cycles dep. on SWL bit) when SSL=’1’.
SIO Frame synchro active level
SSAL = ‘0’
SFS high level active (reset value)
SSAL = ‘1’
SFS low level active
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