ST40RA166
4 System configuration
Module
Addressa
Base
Top
Reference
Reserved: CPU only
registers
CPG
RTC
INTC
TMU
SCIF1
SCIF2
EMU
Reserved
0x1E100000 0x1FBFFFFF
0x1FC00000
0x1FC80000
0x1FD00000
0x1FD80000
0x1FE00000
0x1FE80000
0x1FF00000
0x1FF80000
0x1FC79999
0x1FCFFFFF
0x1FD79999
0x1FDFFFFF
0x1FE79999
0x1FEFFFFF
0x1FF79999
0X1FFFFFFF
Table 1: ST40RA166 system address map (page 2 of 2)
a. For information about which address region to access for each module, see SH-4 32-bit CPU
Core Architecture, sections 2.5 and 3.4.
When operating in privilege mode, these registers should be accessed via the P2 region by
adding an offset of 0xA000 0000, when operating in user mode, access should be via the U0
address.
4.2 System identifiers
q SH-4 core processor identity: 0x0100.
q SH-4 core processor version: 0x0541D.
q ST40RA166-HC8 TAP identity: 05141041.
q ST40RA166-HC8 PCI identity:
Vendor: 104A,
Device: 4000,
Revision ID: 0x01,
Class: 0x4 0000,
Subsystem ID: 0x0000.
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