ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
4 System configuration
ST40RA166
4.3
Note:
Interrupt mapping
For full details on the interrupt controller see ST40 Architecture Manual Volume 1:System.
The mapping of the CPU interrupts is described in Section 4.3.1, Section 4.3.2 and Section 4.3.3.
Some INTEVT codes are shown as reserved in Table 2 and therefore cannot be generated by this
device.
4.3.1 ST40 core interrupt allocation
The allocation of core interrupts is as shown in Table 2.
Interrupt source
INTEVT
code
Interrupt priority
Value
Initial value
IPR
bit numbers
NMI
0x1C0
16
-
-
IRL
IRL3–IRL0 = F
0x200
15
-
-
level
IRL3–IRL0 = E
0x220
14
-
-
encoding
IRL3–IRL0 = D
0x240
13
-
-
IRL3–IRL0 = C
0x260
12
-
-
IRL3–IRL0 = B
0x280
11
-
-
IRL3–IRL0 = A
0x2A0
10
-
-
IRL3–IRL0 = 9
0x2C0
9
-
-
IRL3–IRL0 = 8
0x2E0
8
-
-
IRL3–IRL0 = 7
0x300
7
-
-
IRL3–IRL0 = 6
0x320
6
-
-
IRL3–IRL0 = 5
0x340
5
-
-
IRL3–IRL0 = 4
0x360
4
-
-
IRL3–IRL0 = 3
0x380
3
-
-
IRL3–IRL0 = 2
0x3A0
2
-
-
IRL3–IRL0 = 1
0x3C0
1
-
-
IRL
IRL0
independent IRL1
encoding
IRL2
0x240
15 to 0
13
IPRD[15:12]
0x2A0
15 to 0
10
IPRD[11:8]
0x300
15 to 0
7
IPRD[7:4]
IRL3
0x360
15 to 0
4
IPRD[3:0]
H-UDI
H-UDI
0x600
15 to 0
0
IPRC[3:0]
TMU0
TUNI0
0x400
15 to 0
0
IPRA[15:12]
TMU1
TUNI1
0x420
0 to 15
0
IPRA[11:8]
TMU2
TUNI2
TICPI2
0x440
0 to 15
0
0x460
IPRA[7:4]
Table 2: ST40 core interrupt allocation (page 1 of 2)
Priority
within IPR
setting unit
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
High
Low
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