ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
4 System configuration
ST40RA166
4.3.3 ST40RA166 I/O device interrupt allocation
Interrupt source
Mailbox
Reserved
EMPI
MAILBOX
Reserved
INV_ADDR
Reserved
INTEVT
code
0x1000
0x1380
Interrupt priority
Value
Initial value
IPR
bit numbers
0 to 15
0 to 15
0 to 15
0
INTPRI04[0:3]
0
INTPRI04[27:24]
0
INTPRI04[31:28]
Table 4: Mailbox and EMPI interrupt allocation
Priority
within IPR
setting unit
High to low
High to low
High to low
4.4 GPDMA channel mapping
For full details of the GPDMA controller see ST40 Architecture Manual Volume 1: System.
The ST40RA166 general purpose DMA controller channel map is shown in Table 5.
Request
number
Associated
device
Protocol
Comment
0
1
2 and 3
4
5
6
7
8
9 and 10
11
12
13
14
15 to 31
External device 0
External device 1
Reserved
SCIF1 transmit
SCIF1 received
SCIF2 transmit
SCIF2 receive
TMU
Reserved
PCI1
PCI2
PCI3
PCI4
Reserved
DREQ or
DREQ/DRACK
DREQ or
DREQ/DRACK
DREQ
DREQ
DREQ
DREQ
DREQ/DRACK
DREQ or
DREQ/DRACK
DREQ or
DREQ/DRACK
DREQ or
DREQ/DRACK
DREQ or
DREQ/DRACK
The following pins are available for external peripherals:
DREQ[0:1],
DACK[0:1],
DRAK[0:1].
This allow SCIF to memory and memory to SCIF transfer
to be supported on any DMA channel.
Typically used to trigger or pace memory transfers.
May be used to improve the efficiency of transfers to and
from the PCI.
Table 5: GPDMA request number allocation
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