ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
4 System configuration
ST40RA166
4.7 Memory bridge control
The architecture of the SuperHyway interconnect is shown in Figure 3. Initiators are shown on the
left, and targets are shown on the right of the interconnect. The bit width of the initiator and target
ports are shown in the diagram.
SH core
32
EMPI
Memory
bridge
32
Memory
PCI_ST_I bridge
32
LMI
64
Memory
bridge EMI
32
SuperHyway
Interconnect
Memory
bridge PCI_ST_T
32
GPDMA
32
P
I
32
PER
SH_PER
Figure 3: ST40RA166 interconnect architecture
The ST40RA166 architecture requires seven memory bridges on clock change boundaries.
Memory bridge number
1
2
3
4
5
6
7
SuperHyway type Subsystem
T3
EMI target
T3
EMPI initiator
T1
EMI_SS target
T2
Reserved
T2
Reserved
T3
PCI_ST_I
T3
PCI_ST_T
Table 7: Memory bridges
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