ST70235A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST70235A' PDF : 28 Pages View PDF
ST70235A
Figure 20 : Transmit Interface
MCLK
Tv
AFTXD
Figure 21 : Receive Interface
MCLK
Ts
Th
AFRXD
Tc
CLWD
Table 3 : Transmitted Bits Assigned to Signal /
Time Slot
AFTXD[0]
AFTXD[1]
AFTXD[2]
AFTXD[3]
Cycle 0 Cycle 1 Cycle 2 Cycle 3
b0
b4
b8
b12
b1
b5
b9
b13
b2
b6
b10
b14
b3
b7
b11
b15
Table 4 : Transmitted Bits Assigned to Signal /
Time Slot
AFRXD[0]
AFRXD[1]
AFRXD[2]
AFRXD[3]
Cycle 0 Cycle 1 Cycle 2 Cycle 3
b0
b4
b8
b12
b1
b5
b9
b13
b2
b6
b10
b14
b3
b7
b11
b15
Table 5 : Master Clock (MCLK) AC Electrical Characteristics
Symbol
Parameter
Minimum
Typical
F
Tper
Th
Clock Frequency
Clock Period
Clock Duty Cycle
35.328
28.3
40
Table 6 : AFTXD, AFTXED, CLWD AC Electrical Characteristics
Symbol
Parameter
Minimum
Typical
Tv
Data Valid Time
0
Tc
Data Valid Time
0
Table 7 : AFRXD AC Electrical Characteristics
Symbol
Parameter
Minimum
Typical
Ts
Data setup Time
5
Th
Data hold Time
5
Maximum
60
Maximum
13
10
Maximum
Unit
MHz
ns
%
Unit
ns
ns
Unit
ns
ns
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