ST70235A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST70235A' PDF : 28 Pages View PDF
ST70235A
Tests, Clock, JTAG Interface
– Mclk: Master Clock (35.328MHz) generated by
VCXO
– ATM receive interface, asynchronous clock gen-
erated by Utopia Master
– ATM transmit interface, asynchronous clock
generated by Utopia Master
– ATC clock (Pclk): external asynchronous clock
(synchronous with ATC in case of i960 specific
interface)
JTAG TP interface: Standard Test Access Port,
Used with the boundary scan for chip and board
testing. This JTAG TAP interface consists in 5
signals:
TDI, TDO, TCK & TMS.
TSRTB: Test Reset, reset the TAP controller.
TRSTB is an active low signal.
Table 8 : Boundary Scan Chain Sequence
Signal
Name
Sequence
Number
BS
Type
Ad[0]
IO2
B
Ad[1]
IO3
B
Ad[2]
IO4
B
Ad[3]
IO6
B
Ad[4]
IO7
B
Ad[5]
IO9
B
Ad[6]
IO10
B
Ad[7]
IO12
B
Ad[8]
IO13
B
Ad[9]
IO14
B
Ad[10]
IO16
B
Ad[11]
IO17
B
Ad[12]
IO19
B
Pclk
IO21
C
Ad[13]
IO23
B
Ad[14]
IO24
B
Ad[15]
IO25
B
Be1
IO27
I
Ale
IO28
C
Table 8 : Boundary Scan Chain Sequence
Signal
Name
Csb
Wr_Rdb
Rdyb
Obc_Type
Intb
Resetb
U_Rxdata[0]
U_Rxdata[1]
U_Rxdata[2]
U_Rxdata[3]
U_Rxdata[4]
U_Rxdata[5]
U_Rxdata[6]
U_Rxdata[7]
U_Rxaddr[0]
U_Rxaddr[1]
U_Rxaddr[2]
U_Rxaddr[3]
U_Rxaddr[4]
Gp_In[0]
Gp_In[1]
U_Rxrefb
U_Txrefb
U_Rxclk
U_Rxsoc
U_Rxclav
U_Rxenb
U_Txclk
U_Txsoc
U_Txclav
U_Txenb
U_Txdata[7]
U_Txdata[6]
Sequence
Number
IO30
IO31
IO32
IO33
IO34
IO35
IO38
IO39
IO41
IO42
IO44
IO45
IO47
IO48
IO50
IO51
IO52
IO53
IO55
IO56
IO58
IO60
IO61
IO63
IO64
IO65
IO66
IO68
IO69
IO70
IO71
IO74
IO75
BS
Type
I
I
B
I
O
I
B
B
B
B
B
B
B
B
I
I
I
I
I
I
I
O
I
C
I
O
I
C
I
O
I
I
I
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