ST70235A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST70235A' PDF : 28 Pages View PDF
ST70235A
Table 8 : Boundary Scan Chain Sequence
Signal
Name
U_Txdata[5]
U_Txdata[4]
U_Txdata[3]
U_Txdata[2]
U_Txdata[1]
U_Txdata[0]
U_Txaddr[4]
U_Txaddr[3]
U_Txaddr[2]
U_Txaddr[1]
U_Txaddr[0]
Reserved 0
Reserved 1
Reserved 2
Reserved 3
Reserved 4
Reserved 5
Reserved 6
Reserved 7
Reserved 8
Reserved 9
Reserved 10
Reserved 11
Reserved 12
Reserved 13
Reserved 14
Reserved 15
Reserved 16
TDI
TDO
TMS
TCK
TRSTB
Testse
GP_Out
Sequence
Number
IO77
IO78
IO79
IO80
IO82
IO83
IO84
IO85
IO87
IO88
IO89
IO90
IO92
IO93
IO94
IO96
IO97
IO98
IO99
IO100
IO101
IO103
IO104
IO105
IO106
IO107
IO110
IO111
IO112
IO113
IO114
IO116
IO118
IO119
IO120
BS
Type
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
NONE
O
I
I
I
I
O
O
O
NONE
NONE
NONE
NONE
NONE
C
O
24/28
Table 8 : Boundary Scan Chain Sequence
Signal
Name
Pdown
Afrxd[0]
Afrxd[1]
Afrxd[2]
Afrxd[3]
Clwd
Mclk
Ctrldata
Disable_Comp
Iddq
AFTXD[0]
AFTXD[1]
AFTXD[2]
AFTXD[3]
Sequence
Number
IO121
IO123
IO124
IO125
IO126
IO128
IO129
IO130
IO135
IO138
IO139
IO140
IO142
IO143
BS
Type
O
I
I
I
I
I
C
O
I
C
NONE
NONE
NONE
NONE
General purpose I/O register (0x40)
Field
Type
Position
Bits
Length
Function
GP_IN R
[0,1]
GP_OUT RW
[2]
2 Sampled
level on pins
GP_IN
1 Output level
on pins
GP_OUT
Bits from 3 to 15 are reserved
Reset Initialization
The ST70235A supports two reset modes:
– A 'hardware' reset is activated by the RESETB
pin (active low). A hard reset occurs when a low
input value is detected at the RESETB input.
The low level must be applied for at least 1ms to
guarantee a correct reset operation. All clocks
and power supplies must be stable for
200ns prior to the rising edge of the RESETB
signal.
– 'Soft' reset activated by the controller write
access to a soft reset configuration bit. The reset
process takes less than 10000 MCLK clock
cycles.
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