ST72321BR9-AUTO View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72321BR9-AUTO
STMicroelectronics
'ST72321BR9-AUTO' PDF : 247 Pages View PDF
Interrupts
ST72321Bxxx-Auto
Table 19. Interrupt mapping
No.
Source
block
Description
Register
label
Priority
order
Exit
from
Halt /
Active
Halt
Address
vector
RESET Reset
TRAP Software interrupt
0
TLI External top level interrupt
1 MCC/RTC Main clock controller time base interrupt
2
ei0 External interrupt port A3..0
3
ei1 External interrupt port F2..0
4
ei2 External interrupt port B3..0
5
ei3 External interrupt port B7..4
6
Not used
7
SPI SPI peripheral interrupts
8 TIMER A TIMER A peripheral interrupts
9 TIMER B TIMER B peripheral interrupts
10
SCI SCI peripheral interrupts
11
AVD Auxiliary voltage detector interrupt
12
I2C I2C peripheral interrupts
13 PWM ART PWM ART interrupt
N/A
EICR
MCCSR
Higher
priority
N/A
SPICSR
TASR
TBSR
SCISR
SICSR
Lower
priority
(see
peripheral)
ARTCSR
yes
no
yes
yes
yes
yes
yes
yes
yes(1)
no
no
no
no
no
yes(2)
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
1. Exit from HALT possible when SPI is in slave mode.
2. Exit from HALT possible when PWM ART is in external clock mode.
7.6
7.6.1
External interrupts
I/O port interrupt sensitivity
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register (Figure 21). This control allows to have up to four fully independent external
interrupt source sensitivities.
Each external interrupt source can be generated on four (or five) different events on the pin:
● Falling edge
● Rising edge
● Falling and rising edge
● Falling edge and low level
● Rising edge and high level (only for ei0 and ei2)
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