ST72321BR9-AUTO View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72321BR9-AUTO
STMicroelectronics
'ST72321BR9-AUTO' PDF : 247 Pages View PDF
Interrupts
ST72321Bxxx-Auto
7.6.2 External interrupt control register (EICR)
EICR
Reset value: 0000 0000 (00h)
7
6
5
4
3
2
1
0
IS1[1:0]
IPB
IS2[1:0]
IPA
TLIS
TLIE
RW
RW
RW
RW
RW
RW
Table 20. EICR register description
Bit Name
Function
ei2 and ei3 sensitivity
7:6 IS1[1:0]
The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following
external interrupts:
- ei2 (port B3..0) (see Table 21)
- ei3 (port B7..4) (see Table 22)
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1
(level 3).
Interrupt polarity for port B
5 IPB
This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It can
be set and cleared by software only when I1 and I0 of the CC register are both set
to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following
external interrupts:
4:3 IS2[1:0] - ei0 (port A3..0) (see Table 23)
- ei1 (port F2..0) (see Table 24)
These 2 bits can be written only when I1 and I0 of the CC register are both set to 1
(level 3).
Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It can
2 IPA
be set and cleared by software only when I1 and I0 of the CC register are both set
to 1 (level 3).
0: No sensitivity inversion
1: Sensitivity inversion
TLI sensitivity
This bit allows to toggle the TLI edge sensitivity. It can be set and cleared by
1 TLIS
software only when TLIE bit is cleared.
0: Falling edge
1: Rising edge
TLI enable
This bit allows to enable or disable the TLI capability on the dedicated pin. It is set
0 TLIE
and cleared by software.
0: TLI disabled
1: TLI enabled
Note: A parasitic interrupt can be generated when clearing the TLIE bit.
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