ST72P314J2T View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72P314J2T
STMicroelectronics
'ST72P314J2T' PDF : 153 Pages View PDF
ST72334J/N, ST72314J/N, ST72124J
4.4 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION
CLOCK RESET AND SUPPLY REGISTER
(CRSR)
Read / Write
Reset Value: 000x 000x (00h)
7
0
0
0
0
LVD
RF
0
CSS CSS WDG
IE D RF
Bit 7:5 = Reserved, always read as 0.
Bit 1 = CSSD Clock security system detection
This bit indicates that the safe oscillator of the
Clock Security System block has been selected by
hardware due to a disturbance on the main clock
signal (fOSC). It is set by hardware and cleared by
a read of the CRSR register when the original os-
cillator recovers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by OPTION BYTE, the
CSSD bit value is forced to 0.
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or a LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
Bit 3 = Reserved, always read as 0.
Bit 2 = CSSIE Clock security syst. interrupt enable
This bit enables the interrupt when a disturbance
is detected by the Clock Security System (CSSD
bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
When the CSS is disabled by OPTION BYTE, the
CSSIE bit has no effect.
RESET Sources
External RESET pin
Watchdog
LVD
LVDRF
0
0
1
WDGRF
0
1
X
Application notes
In case the LVDRF flag is not cleared upon anoth-
er RESET type occurs (extern or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this condition, a watchdog reset can be detect-
ed by the software while an external reset not.
Table 4. Clock, Reset and Supply Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
002Bh
CRSR
Reset Value
0
0
LVDRF
0
x
0
CFIE
0
CSSD WDGRF
0
x
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