ST72334J/N, ST72314J/N, ST72124J
INTERRUPTS (Cont’d)
Figure 26. Interrupt Processing Flowchart
FROM RESET
N
BIT I SET
Y
FETCH NEXT INSTR UCTION
N
BIT I SET
Y
N
EXECU TE INSTRUCTION
IRET
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTO R
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 6. Interrupt Mapping
N°
Source
Block
Description
RESET Reset
TRAP
Software Interrupt
0
Not used
1
MCC
CSS
Main Clock Controller Time Base Interrupt
or Clock Security System Interrupt
2
EI0
External Interrupt Port A3..0
3
EI1
External Interrupt Port F2..0
4
EI2
External Interrupt Port B3..0
5
EI3
External Interrupt Port B7..4
6
Not used
7
SPI
SPI Peripheral Interrupts
8
TIMER A TIMER A Peripheral Interrupts
9
TIMER B TIMER B Peripheral Interrupts
10
SCI
SCI Peripheral Interrupts
11 Data-EEPROM Data EEPROM Interrupt
12
Not used
13
Register
Label
N/A
Priority
Order
Highest
Priority
Exit
from
HALT
yes
no
MCCSR
yes
CRSR
N/A
SPISR
no
TASR
TBSR
SCISR
EECSR
Lowest
Priority
Address
Vector
FFFE h-FFFFh
FFFC h-FFFDh
FFFA h-FFF Bh
FFF8 h-FFF9h
FFF6 h-FFF7h
FFF4 h-FFF5h
FFF2 h-FFF3h
FFF0 h-FFF1h
FFEEh-FFE Fh
FFECh-FFE Dh
FFEA h-FFE Bh
FFE8h-FFE 9h
FFE6h-FFE 7h
FFE4h-FFE 5h
FFE2h-FFE 3h
FFE0h-FFE 1h
37/125