ST72P314J2T View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72P314J2T
STMicroelectronics
'ST72P314J2T' PDF : 153 Pages View PDF
ST72334J/N, ST72314J/N, ST72124J
POWER SAVING MODES (Cont’d)
Standard HALT mode
In this mode the main oscillator is turned off caus-
ing all internal processing to be stopped, including
the operation of the on-chip peripherals. All periph-
erals are not clocked except the ones which get
their clock supply from another clock generator
(such as an external or auxiliary oscillator).
The compatibility of Watchdog operation with Halt
mode is configured by the “WDGHALT” option bit
of the OPTION BYTE. The HALT instruction when
executed while the Watchdog system is enabled,
can generate a Watchdog RESET (see dedicated
section for more details).
When exiting HALT mode by means of a RESET
or an interrupt, the oscillator is immediately turned
on and the 4096 CPU cycle delay is used to stabi-
lize the oscillator.
Figure 29. HALT modes flow-chart
Specific ACTIVE-HALT mode
As soon as the interrupt capability of the main os-
cillator is selected (OIE bit set), the HALT instruc-
tion will make the device enter a specific ACTIVE-
HALT power saving mode instead of the standard
HALT one.
This mode consists of having only the main oscil-
lator and its associated counter running to keep a
wake-up time base. All other peripherals are not
clocked except the ones which get their clock sup-
ply from another clock generator (such as external
or auxiliary oscillator).
The safeguard against staying locked in this AC-
TIVE-HALT mode is insured by the oscillator inter-
rupt.
Note: As soon as the interrupt capability of one of
the oscillators is selected (OIE bit set), entering in
ACTIVE-HALT mode while the Watchdog is active
does not generate a RESET.
This means that the device cannot to spend more
than a defined delay in this power saving mode.
If WDGHA LT
bit reset in
OPTION BYTE
HALT INSTR UCTION
HALT
N
WAT CHDOG
Y
ENA BLE
OSCI LLATOR
PER IPHERAL S
CPU
I BIT
OFF
OFF
OFF
0
0
MAIN
1
OSC ILLATOR
OIE BIT
ACTIV E-HALT
O SCILLATO R
PERIPH ERALS
CPU
I BIT
ON
OFF
OFF
0
N
N
EXTE RNAL*
INTERRUP T
Y
RESET
Y
OSCILLAT OR
PERIP HERALS
CPU
4096 clock cycles delay
ON
OFF
OFF
O SCILLATO R
ON
PERIPH ERALS
ON
CPU
ON
FETCH RESET VECTOR
OR SERVICE INTERRUPT **
Notes:
* External interrupt or internal interrupts with Exit from Halt Mode capability
** Before servicing an interrupt, the CC register is pushed on the stack.
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