ST72P314J2T View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST72P314J2T
STMicroelectronics
'ST72P314J2T' PDF : 153 Pages View PDF
ST72334J/N, ST72314J/N, ST72124J
MAIN CLOCK CONTROLLER (Cont’d)
MISCELLANEOUS REGISTER 1 (MISCR1)
See section 6.2 on page 47.
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read / Write
Reset Value: 0000 0001 (01h)
7
0
0
0
0
0 TB1 TB0 OIE OIF
Bit 7:4 = Reserved, always read as 0.
Bit 3:2 = TB1-TB0 Time base control
These bits select the programmable divider time
base. They are set and cleared by software.
Coun ter
Prescaler
Time Base
fOSC =8MHz fOSC=16MHz
TB1
TB0
32000
4ms
2ms
0
0
64000
8ms
4ms
0
1
160000
20ms
10ms
1
0
400000
50ms
25ms
1
1
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid unwanted time shift. This allows to
use this time base as a real time clock.
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt allows to exit from ACTIVE-HALT
mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode.
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has measured the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
Warning: The BRES and BSET instructions must
not be used on the MCCSR register to avoid unin-
tentionally clearing the OIF bit.
Table 5. MCC Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
0029h
MCCSR
Reset Value
0
0
0
4
3
2
1
0
TB1
TB0
OIE
OI F
0
0
0
0
1
35/125
Share Link: 