ST7FDALI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FDALI
STMicroelectronics
'ST7FDALI' PDF : 141 Pages View PDF
ST7DALI
DALI COMMUNICATION MODULE (Cont’d)
11.4.10 Bi-phase Bit Detection
The clock used for sampling the DALI signal is pro-
grammed by the DCMCLK register. Each bit
phase is sampled 16 times. The bit phase level is
determined by two of three sample clock pulses
(pulses 6,7,8). The two phase levels of the bi-
phase bit are shifted into the 4-bit pre-shift register
at the 9th sample clock pulse.
Figure 43. DALI Signal Sampling
Only the second phase level of the bi-phase bit is
shifted into the 16-bit shifter.
The 4-bit pre-shifter is used to detect any errors in
the received frame.
When a change of phase is detected (edge trig-
ger), the 4-bit sample clock counter (integer range
0 to15) is cleared.
DALI Signal
4-bit sample clock counter
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Phase Detector
Shifter Clock
4-bit Pre-shifter
x
0
16-bit Shifter
xxxx
Edge Trigger
01
xxx1
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