ST7FDALI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FDALI
STMicroelectronics
'ST7FDALI' PDF : 141 Pages View PDF
ST7DALI
DALI COMMUNICATION MODULE (Cont’d)
11.4.11 Register Description
DCM DATA RATE CONTROL REGISTER
(DCMCLK)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
CK7 CK6 CK5 CK4 CK3 CK2 CK1 CK0
Bits 7:0 = DCMCLK[7:0] Clock Prescaler.
These bits are set/cleared by software and cleared
by hardware after a reset.
These 8 bits are used for tuning the DALI data
rate. fDATA = fCPU/[(N+1)*16] where N is the inte-
ger value of the DCMCLK register.
DCM FORWARD ADDRESS REGISTER
(DCMFA)
Read only
Reset Value: 0000 0000 (00h)
7
0
FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0
Bits 7:0 = DCMFA[7:0] Forward Address.
These bits are read by software and set/cleared by
hardware.
These 8 bits are used to store the "forward frame"
address byte.
DCM FORWARD DATA REGISTER (DCMFD)
Read only
Reset Value: 0000 0000 (00h)
7
0
FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0
Bits 7:0 = DCMFD[7:0] Forward Data.
These bits are read by software and set/cleared by
hardware.
These 8 bits are used to store the "forward frame"
data byte.
DCM BACKWARD DATA REGISTER (DCMBD)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0
Bits 7:0 = DCMBD[7:0] Backward Data.
These bits are set/cleared by software and cleared
by hardware after a reset.
These 8 bits are used to store the "backward
frame" data byte. The sofware writes to this regis-
ter before enabling the transmit operation.
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