ST7DALI
DALI COMMUNICATION MODULE (Cont’d)
In the example shown in Figure 44, the DCMC-
SR[3:0] bits are updated automatically at each
edge trigger (DALI signal change of phase). At the
same time the value of the 4-bit sample clock
counter is reset. By reading the DCMCSR[3:0] bits
software can detect changes in the DALI signal
pulse length.
Figure 44. Example of DALI Signal Sampling
833.33µs
DALI Signal
Edge Trigger
tCPU
tCPU
tCPU
4-bit sample
clock counter
(/16 divider)
m
0000 0001
1111 0000
xxxx 0000
DCMCSR[3:0]
bits
0000
Legend:
1
tCPU= fCPU
m = (DCMCLK integer value+1) x tCPU
Example:
fDALI= 1.2 kHz
fCPU= 8 MHz
N = 207 (DCMCLK)
tCPU = 125ns
1111
m = 26 µs (208 x 125ns)
xxxx
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