ST7FLITE02Y1B6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLITE02Y1B6
STMicroelectronics
'ST7FLITE02Y1B6' PDF : 124 Pages View PDF
ST7LITE0xY0, ST7LITESxY0
ADC CHARACTERISTICS (Cont’d)
Figure 82. RAIN max. vs fADC with CAIN=0pF1)
Figure 83. Recommended CAIN/RAIN values2)
45
1000
40
Cain 10 nF
4 MHz
35
100
Cain 22 nF
30
2 MHz
Cain 47 nF
25
1 MHz
10
20
15
10
1
5
0
0
10
30
70
0.1
0.01
0.1
1
10
CPARASITIC (pF)
fAIN(KHz)
Notes:
1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
2. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization and to allow
the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤ 4MHz.
13.11.1 General PCB Design Guidelines
To obtain best results, some general design and
layout rules should be followed when designing
the application PCB to shield the noise-sensitive,
analog physical interface from noise-generating
CMOS logic signals.
Properly place components and route the signal
traces on the PCB to shield the analog inputs. An-
alog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signals from digital signals that may switch
while the analog inputs are being sampled by the
A/D converter. Do not toggle digital outputs on the
same I/O port as the A/D input being converted.
105/124
Share Link: 