ST7FLITE29 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLITE29
STMicroelectronics
'ST7FLITE29' PDF : 133 Pages View PDF
ST7LITE2
OPERATING CONDITIONS (Cont’d)
13.3.4.2 RC oscillator and PLL characteristics (tested for TA = -40 to +85°C) @ VDD = 2.7 to 3.3V
Symbol
Parameter
Conditions
Min Typ Max Unit
fRC 1)
Internal RC oscillator fre- RCCR = FF (reset value), TA=25°C, VDD= 3.0V
quency 1)
RCCR=RCCR13) ,TA=25°C,VDD= 3V
560
700
kHz
Accuracy of Internal RC TA=25°C,VDD=3V
-2
+2 %
ACCRC
oscillator when calibrated
with RCCR=RCCR12)3)
TA=25°C,VDD=2.7 t 3.3V
TA=-40 to +85°C,VDD=3V
-25
+25 %
-15
15 %
IDD(RC)
RC oscillator current con-
sumption
TA=25°C,VDD=3V
7002)
µA
tsu(RC)
fPLL
tLOCK
tSTAB
ACCPLL
tw(JIT)
JITPLL
IDD(PLL)
RC oscillator setup time
x4 PLL input clock
PLL Lock time6)
PLL Stabilization time6)
TA=25°C,VDD=3V
x4 PLL Accuracy
fRC = 1MHz@TA=25°C,VDD=2.7 to 3.3V
fRC = 1MHz@TA=40 to +85°C,VDD= 3V
PLL jitter period
fRC = 1MHz
PLL jitter (∆fCPU/fCPU)
PLL current consumption TA=25°C
0.72)
103) µs
MHz
2
ms
4
ms
0.15)
%
0.15)
%
1254)
µs
14)
%
1902)
µA
Notes:
1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.
2. Data based on characterization results, not tested in production
3. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 23.
4. Guaranteed by design.
5. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy
6. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 12 on page 24.
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