ST7FLITE29 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLITE29
STMicroelectronics
'ST7FLITE29' PDF : 133 Pages View PDF
ST7LITE2
13.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).
13.4.1 Supply Current
TA = -40 to +85°C unless otherwise specified, VDD=5.5V
Symbol
Parameter
Supply current in RUN mode
Supply current in WAIT mode
IDD
Supply current in SLOW mode
Supply current in SLOW WAIT mode
Supply current in HALT mode 5)
Supply current in AWUFH mode 6)7)
Conditions
External Clock, fCPU=1MHz 1)
Internal RC, fCPU=1MHz
fCPU=8MHz 1)
External Clock, fCPU=1MHz 2)
Internal RC, fCPU=1MHz
fCPU=8MHz 2)
fCPU=250kHz 3)
fCPU=250kHz 4)
-40°C≤TA≤+85°C
TA= +125°C
TA= +25°C
Typ Max Unit
1
2.2
7.5
12
0.8
mA
1.8
3.7
6
1.6
2.5
1.6
2.5
1
10
15
50
µA
20
30
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals
in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)
driven by external square wave, LVD disabled.
3. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
4. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at
VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
5. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,
tested in production at VDD max and fCPU max.
6. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU
max.
7. This consumption refers to the Halt period only and not the associated run period which is software dependent.
Figure 60. Typical IDD in RUN vs. fCPU
9.0
8.0
8Mhz
7.0
4Mhz
6.0
1Mhz
5.0
4.0
3.0
2.0
1.0
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Vdd (V)
Figure 61. Typical IDD in SLOW vs. fCPU
1.6
1.4
250Khz
1.2
125Khz
1.0
62.5Hz
0.8
0.6
0.4
0.2
0.0
2 2.5 3 3.5 4 4.5 5 5.5 6
Vdd (V)
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