ST7LITE2
OPERATING CONDITIONS (Cont’d)
Figure 57. PLL ∆fCPU/fCPU versus time
∆fCPU/fCPU
Max
t
0
Min
tw(JIT)
tw(JIT)
Figure 58. PLLx4 Output vs CLKIN frequency
7.00
6.00
5.00
3.3
4.00
3
3.00
2.7
2.00
1.00
1
1.5
2
2.5
3
External Input Clock Frequency (MHz)
Note: fOSC = fCLKIN/2*PLL4
Figure 59. PLLx8 Output vs CLKIN frequency
11.00
9.00
7.00
5.5
5
5.00
4.5
4
3.00
1.00
0.85 0.9
1
1.5
2
2.5
External Input Clock Frequency (MHz)
Note: fOSC = fCLKIN/2*PLL8
13.3.4.3 32MHz PLL
TA = -40 to 85°C, unless otherwise specified
VDD
fPLL32
fINPUT
Symbol
Parameter
Voltage 1)
Frequency 1)
Input Frequency
Note 1: 32 MHz is guaranteed within this voltage range.
Min
Typ
4.5
5
32
7
8
Max
Unit
5.5
V
MHz
9
MHz
98/133
1