ST7FLU05MCE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLU05MCE
STMicroelectronics
'ST7FLU05MCE' PDF : 124 Pages View PDF
ST7LUS5, ST7LU05, ST7LU09
On-chip peripherals
Table 48. ADCCSR register description (continued)
Bit Name
Function
Channel selection
These bits are set and cleared by software. They select the analog input to convert
as follows:
2:0 CH[2:0]
000: Channel pin = AIN0
001: Channel pin = AIN1
010: Channel pin = AIN2
011: Channel pin = AIN3
100: Channel pin = AIN4
Note: A write to the ADCCSR register (with ADON set) aborts the current
conversion, resets the EOC bit and starts a new conversion.
) Data register high (ADCDRH)
ct(s ADCDRH
du 7
6
5
4
3
ro ) D[9:2]
P t(s RO
lete duc Table 49. ADCDRH register description
so ro Bit Name
Function
b P 7:0 D[9:2] MSB of analog converted value
) - O lete Data register low (ADCDRL)
Reset value: 0000 0000 (00h)
2
1
0
ct(s bso ADCDRL
Produ t(s) - O 7
6
5
Reserved
-
Reset value: 0000 0000 (00h)
4
3
2
1
0
SLOW Reserved
D[1:0]
R/W
-
R/W
lete duc Table 50. ADCDRL register description
so ro Bit Name
Function
b P 7:4 - Reserved, forced by hardware to 0
O te Slow mode
le3 SLOW This bit is set and cleared by software. It is used together with the SPEED bit in the
so ADCCSR register to configure the ADC clock speed as shown in Table 52.
Ob 2
- Reserved, forced by hardware to 0
1:0 D[1:0] LSB of analog converted value
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